Polyphase Multipath Circuits for Cognitive Radio and Flexible Multi- Phase Clock Generation

In this chapter we discuss flexible cognitive radio circuits for dynamic access of unused spectrum. Ideally, such circuits can work at an arbitrary radio frequency (RF). We review techniques to realize radios without resorting to frequency selective dedicated filters [24], in particular a recently proposed polyphase multipath technique canceling harmonics and sidebands [11,12]. Using this technique, a wideband and flexible power upconverter with a clean output spectrum can be realized on a CMOS chip, aiming at flexible radio transmitter applications. Prototype chips can transmit at an arbitrary frequency between DC and 2.4GHz. Unwanted harmonics and sidebands are more than 40dB lower then the desired signal up to the 17th harmonic of the transmit frequency. Such polyphase multipath circuits need flexible multi-phase clocking with a large frequency range and low phase errors. We will compare a Shift Register (SR) to a Delay Locked Loop (DLL) for multi-phase clock generation, and motivate why a SR is not only more flexible but often also better [16]. For a given power budget, we show that a SR almost always generates less jitter than a DLL, assuming both are realized with current mode logic. This is due to differences in jitter accumulation and the possibility to choose latch delays in a SR much smaller than the delays of DLL elements. For N-phase clock generation, a SR also functions as a divide-by-N and requires a VCO with N times higher frequency. However, this does not necessarily lead to more power consumption and can even have advantages like higher Q and less area for the inductors.